Voltage controlled oscillator with common mode adjustment start-up

ABSTRACT

The present disclosure provides methods and apparatus for dynamically adjusting the common mode voltage at the LC tank node and/or the power supply voltage of a VCO with an LC resonator in order to force oscillation start-up by temporarily increasing gain. Methods according to certain preferred embodiments may reduce power consumption and/or overcome threshold voltage limitations and/or increase frequency and frequency tuning range during normal (steady-state) operation.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 14/744,756, filed Jun. 19, 2015, which is a continuationapplication of U.S. patent application Ser. No. 14/160,375 filed Jan.21, 2014 and entitled VOLTAGE CONTROLLED OSCILLATOR WITH COMMON MODEADJUSTMENT START-UP, which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to voltage controlled oscillators (VCOs)and a method of and an apparatus for operating a VCO. In particular, itrelates to a VCO and a method of dynamically adjusting the common modevoltage at the LC tank node and/or the power supply voltage of a VCOwith an LC resonator in order to force oscillation start-up bytemporarily increasing gain, thereby reducing power consumption and/orovercoming threshold voltage limitations and/or increasing the frequencyand frequency tuning range during normal (steady-state) operation.

BACKGROUND

The Phase Locked Loops (PLLs) in general, and a special class of PLLsknown as Clock Synthesizer Units (CSUs), require Voltage ControlledOscillators (VCOs) to generate an output clock signal, where thefrequency of the output clock signal is proportional to an input controlvoltage. The VCO must start-up reliably in order to guarantee CSUstability in the steady-state. Failure of the VCO to start-up reliablywill result in a non-functional PLL/CSU.

One known method of implementing a VCO is the complementarycross-coupled LC-oscillator, described by Craninckx et al, in, “A fullyintegrated spiral-LC CMOS VCO set with prescaler for GSM and DCS-1800systems,” in Proc. IEEE Custom Integrated Circuits Conference (CICC),May 1997, pp. 403-406. A phase noise analysis of this type of VCO wascarried out by Hajimiri et al. in, “Design Issues in CMOS DifferentialLC Oscillators,” in J. Solid-State Circuits, Vol. 34, No. 5, May 1999,pp. 717-724. Hajimiri et al. showed that this type of oscillator offersa number of advantages over NMOS-only or PMOS-only structures,including: higher transconductance (g_(m)) for a given current andtherefore faster switching, and better rise-and fall-time symmetryresulting in a smaller 1/f³ flicker phase noise with lower flickercorner frequency. Given these advantages, the VCO core described in theabove papers is used for the present invention, though it should benoted that the invention could be used with other architectures.

FIG. 1 is a diagram showing the architecture of an example of a wellknown complementary cross-coupled LC VCO 10, as described in thereferences above. The example VCO 10 includes a cross-coupled pair ofPMOS transistors 11 and 12, and a cross-coupled pair of NMOS transistors13 and 14. The cross-coupled transistor devices 11, 12, 13 and 14 setthe common mode voltage, V_(CM)=(V₊+V⁻)/2. Ideally, the devices are wellmatched and common mode voltage is equivalent to half the supply voltage(i.e. V_(CM)=V_(DD)/2 in FIG. 1). Frequency selectivity is provided by afixed inductor (L) 15 and a variable capacitor (C) 16, where thecapacitor is controlled using analog voltage and/or digital selection.The inductor 15 and capacitor 16 are sometimes referred to as the “LCtank”.

The gain of cross-coupled devices 11-14 must be sufficiently large toguarantee start-up of the VCO. Gain is dependent on devicetransconductance, which in turn is proportional to device width (W) andgate overdrive-voltage, where overdrive-voltage is the voltage betweengate and source in excess of the transistor threshold (turn-on) voltage.Once steady-state has been reached in the LC VCO, only a small amount ofenergy need be injected each cycle to compensate for tank losses.

In low-voltage deep submicron CMOS technologies, circuit power reductionis often achieved by reducing supply voltage. In traditional CMOStechnology scaling, the reduction in power supply voltage is assumed tobe accompanied by a reduction in device threshold voltage. Morerecently, however, when device feature sizes (mainly minimum channellength L_(min)) shrink in each new generation of CMOS technology thedevice threshold voltages may be held steady or increased slightly tofurther reduce power drawn from the supply, reduce power wasted bydrain-source leakage in the off-state, and improve digital circuit noisemargin. As a consequence, the supply voltage for a complementarycross-coupled VCO will have a lower limit determined by the fact thatthe common mode voltage across balanced complementary PMOS or NMOS pairsmust be at least equal to the corresponding transistor thresholdvoltage(s) to avoid significant reductions in device transconductance,and in turn decreases in regenerative loop gain in a VCO such that thegain is no longer sufficient to guarantee the oscillation start-up.

To overcome this limitation, alternative VCO architectures may be used.For example, an NMOS-only (or PMOS-only) VCO structure does not requirea half-supply common mode voltage, offering more flexibility in design.However, the use of this type of VCO means the advantages listed abovefor the complementary cross-coupled structure are lost. Moreover, theremaining NMOS (or PMOS) transistors in the circuit can be subject toelectrical over-stress (EOS) of voltage, a condition that will degradelong-term reliability and lifetime of the device.

Transconductance can be increased somewhat by increasing device width(W), but the impact of increasing width is diminished when common modevoltage across PMOS or NMOS pair is less than the correspondingtransistor threshold voltage, as devices in this case will be biased inthe sub-threshold regime. At the same time, increasing width addsadditional capacitive parasitics to the VCO tank, thereby reducingfrequency tuning range and/or reducing maximum oscillating frequency ofthe VCO.

The inventors have determined a need for methods and apparatus forincreasing the robustness of oscillation start-up reliability withoutimpacting VCO frequency tuning range and in which the advantages of thecross-coupled VCO are retained.

SUMMARY

The present disclosure provides methods and apparatus for dynamicallyadjusting the common mode voltage at the LC tank node and/or the powersupply voltage of a VCO with an LC resonator in order to forceoscillation start-up by temporarily increasing gain. Methods accordingto certain preferred embodiments may reduce power consumption and/orovercome threshold voltage limitations during normal (steady-state)operation.

One aspect provides a method of controlling a voltage controlledoscillator (VCO) having an LC tank and at least one pair of transistorscross-coupled across a pair of common nodes of the LC tank, with a drainof one transistor of the pair and a gate of the other transistor of thepair connected to one of the pair of common nodes of the LC tank, and agate of the one transistor of the pair and a drain of the othertransistor of the pair of transistors connected to the other of the pairof common nodes of the LC tank. The method comprises providing a supplyvoltage to the VCO such that a voltage difference between a common modevoltage at the pair of common nodes and a source voltage of transistorsof the pair of transistors is less than a threshold voltage of thetransistors of the pair of transistors; temporarily adjusting the commonmode voltage to increase the voltage difference and initiate oscillationin the VCO at the common nodes; and, during steady-state oscillation,powering the VCO with the supply voltage.

Another aspect provides an apparatus comprising a voltage controlledoscillator (VCO) having an LC tank and at least one pair of transistorscross-coupled across a pair of common nodes of the LC tank, with a drainof one transistor of the pair and a gate of the other transistor of thepair connected to one of the pair of common nodes of the LC tank, and agate of the one transistor of the pair and a drain of the othertransistor of the pair of transistors connected to the other of the pairof common nodes of the LC tank. A supply voltage is connected to powerthe VCO during steady-state oscillation such that a voltage differencebetween a common mode voltage at the pair of common nodes and a sourcevoltage of transistors of the pair of transistors is less than athreshold voltage of the transistors of the pair of transistors. Acontrol circuit is connected to monitor the pair of common nodes andtemporarily adjust the common mode voltage to increase the voltagedifference and initiate oscillation in the VCO at the common nodes.

Further aspects and details of example embodiments are described below.

DRAWINGS

The following figures set forth embodiments in which like referencenumerals denote like parts. Embodiments are illustrated by way ofexample and not by way of limitation in the accompanying figures.

FIG. 1 shows a complementary cross-coupled VCO according to the priorart.

FIG. 2 shows a complementary cross-coupled VCO with common modeadjustment according to one embodiment.

FIG. 3 shows a complementary cross-coupled VCO with common modeadjustment according to another embodiment.

FIG. 4A shows an NMOS-only cross-coupled VCO with common mode adjustmentaccording to another embodiment.

FIG. 4B shows a PMOS-only cross-coupled VCO with common mode adjustmentaccording to another embodiment.

FIG. 5 is a flowchart illustrating a method of controlling acomplementary cross-coupled VCO with common mode adjustment according toone embodiment.

DETAILED DESCRIPTION

The present disclosure enables the construction of voltage controlledoscillators that demonstrate robust start-up in the presence of unwantedProcess, Voltage, and Temperature (PVT) variations by providingmechanisms to guarantee oscillator start-up using a method that haslittle impact on oscillator device sizing, frequency, phase noise, orpower consumption during normal steady-state operation. The followingdescribes methods and apparatus for increasing the regenerative loopgain of a complementary cross-coupled VCO during start-up. This may beaccomplished by temporarily adjusting the VCO's common mode voltageand/or power supply voltage and/or bias current. Once the VCO is insteady-state oscillation, the nominal steady-state common mode voltageacross the transistor pair can be less than the threshold voltage of thetransistors, since at least part of each oscillation will result in aninstantaneous voltage across the transistors sufficient to enableconduction.

When implemented in a CMOS integrated circuit (IC) technology, the gainboosted during start-up makes it possible for either (a) the use ofPMOS/NMOS transistors with smaller width and/or higher thresholdvoltage, (b) reduced power supply voltage during steady-state operation,or (c) a combination of these features. This can save power and increasethe Frequency Tuning Range (FTR) of the VCO. This method does not impactthe oscillator's frequency or phase noise during normal (steady-state)operation.

Some embodiments provide a voltage-controlled oscillator that consistsof a complementary differential cross-coupled oscillator core, aninductor, a digitally programmable capacitor, and a voltage-controlledvariable capacitor (varactor). A control circuit forces a temporarycommon mode and/or differential voltage change (i.e. increase ordecrease) in the oscillator core, for example by utilizing weak pull-upand/or pull-down transistor devices.

Methods according to preferred embodiments can advantageously be used tochange the common mode level at the VCO signal terminals such thatcommon mode voltage across the cross-coupled NMOS and/or PMOS pair(s)exceeds the threshold voltage of the corresponding transistor devices.This increases transconductance of the respective devices, and in turntheir gain, such that the VCO will start up even when the thresholdvoltage is greater than the nominal steady-state common mode voltageacross the transistor pair (e.g., half the supply voltage in a VCOhaving an architecture like FIG. 1). Once in steady-state, the forcingvoltage is removed and the common mode voltage returns to its originalsub-threshold level. However, given the oscillator is now oscillating insteady-state, each oscillation cycle will present for some percentage ofthe period an instantaneous voltage across the transistor device(s)large enough to enable conduction and thus inject energy back into theLC tank to compensate for losses, hence sustaining the oscillation.

This increased robustness is critical when designing in advanceddeep-submicron digital processes with small geometries, such as 28 nmCMOS and below, as the lowest cost and most resilient digital devices inthese technologies exhibit relatively large threshold voltages thatwould otherwise prevent VCO start-up. In addition, the proposedtemporary shift in common mode voltage to increase start-up gaincircumvents the need for larger core transistors and/or a higher supplyvoltage. Avoiding larger transistors helps reduce parasitic capacitanceloading on the LC tank and hence increases the VCO frequency andfrequency tuning range. Avoiding higher supply voltages helps reduce thepower consumption in a low-power design.

Another advantage of methods and circuits according to certainembodiments is that the common mode adjustment can be tailored toprocess-specific threshold voltages. For example, if in a given devicefabrication lot the process variation causes the threshold voltage ofthe PMOS transistors to be significantly greater than that of the NMOStransistors, a downward pulse with optimum voltage level (i.e. atemporary decrease in common-mode voltage V_(CM)) should be mostsuitable to increase start-up gain by increasing PMOS gate-sourcevoltage. Alternatively, if in a given device fabrication lot thethreshold voltage of the NMOS is greater than the PMOS then an upwardpulse with optimum voltage level (i.e. a temporary increase incommon-mode voltage V_(CM)) should be more suitable for the oscillationstart-up by increasing NMOS gate-source voltage.

For simplicity and clarity of illustration, reference numerals may berepeated among the figures to indicate corresponding or analogouselements. Numerous details are set forth to provide an understanding ofthe examples described herein. The examples may be practiced withoutthese details. In other instances, well-known methods, procedures, andcomponents are not described in detail to avoid obscuring the examplesdescribed. The description is not to be considered as limited to thescope of the examples described herein.

FIG. 2 shows an example circuit 200 according to one embodiment, whichis implemented as a complementary cross-coupled LC-VCO withpull-up/pull-down devices for common mode adjustment and/or gainboosting. The differential VCO core 110 comprises transistors 111, 112,113 and 114, which generate negative resistance required for oscillationthat cancels out positive resistance associated with losses in the LCtank 115, 116. Switching devices 111, 112 and 113, 114 are the PMOS andNMOS halves of the VCO respectively, and each set forms a cross-coupledpair connected between common nodes 117 and 118. The input impedance ofthese cross-coupled pairs exhibits an equivalent negative resistance,whose absolute value is inversely proportional to their respectivetransconductance g_(m).

The VCO output signals at the nodes 117 and 118 are differential, withV₊ the positive output terminal of the VCO and V the negative outputterminal of the VCO. As described earlier, the common mode level of theVCO core 110, V_(CM)=(V₊+V⁻), is set by the relative sizing of the PMOSand NMOS switching devices and by the bias current in the core. Thecurrent in the VCO core 110 is optionally set by gain control circuitry(e.g. amplitude control blocks 130 and 132). For optimum VCO phase noiseperformance the common mode voltage is approximately half the supplyvoltage, or half the supply voltage less the voltage drop across of theamplitude control circuitry 130 or 132.

The inductor 115 and variable capacitor 116 form the VCO'sfrequency-selective tank. The inductor 115 is preferably, but notnecessarily, symmetrical. The variable capacitor 116 is preferably, butnot necessarily, a combination of digitally programmable fixedcapacitances and continuously variable capacitors (varactors).

A pair of pull-up transistors 121 and 122 are connected between voltageterminals V₊ and V⁻ and V_(DD), and a pair of pull-down transistors 123and 124 are connected between voltage terminals V₊ and V⁻ and ground.During steady-state operation, these devices 121-124 are turned off andconsume no power. Devices 121-124 are preferably sized to minimize theimpact of parasitic capacitance on VCO frequency tuning range. Thepull-up/pull-down combination is also sized to balance loading on V₊ andV⁻. Metal connection to the drain terminal of these devices is minimizedto offer low parasitic loading impact on the LC tank. Variousconsiderations may be taken into account to determine suitable sizes fordevices 121-124, depending on the situation. For example, the larger thesize of the pull-up/pull-down devices 121-124, the larger the DC currentwill be through the devices, and the larger the DC current, the largerthe magnitude of the shift in common mode voltage. The devices 121-124are preferably only large enough to shift the common mode voltage by theappropriate amount (the appropriate amount being enough to start up theoscillation and no more). Any additional shift in common mode isunnecessary. Further, the devices 121-124 are preferably sized largeenough to ensure that the DC/AC current though the devices duringstart-up does not exceed reliability limits (too much current in adevice that is too small could lead to damage and degrade the lifetimeof the transistor).

Each of the transistors 121-124 may be a single device, or a combinationof a plurality of parallel devices. When a combination of paralleldevices is used, multiple control signals are applied to each of 121-124so that the magnitude of common mode voltage change at V₊ and V⁻ aremore finely controllable. Equivalent ‘on’ resistance of these devices ispreferably small enough to provide a significant common mode shift butlarge enough not to degrade LC tank quality factor (Q) to the pointwhere no oscillation can occur.

Gate voltages for the pull-up/pull-down devices 121-124 are provided bydigital control and envelope detectors 134 and 136. These detectors 134,136 generate the up/down control signals that drive thepull-up/pull-down devices to ‘on’ and ‘off’ states to fulfill therequired common mode adjustment during the start-up sequence. Thedigital control and envelope detectors 134 and 136 may comprise, forexample, envelope detector circuits which receive the outputs V₊ and V⁻,digital control circuits which provide the gate voltages for thepull-up/pull-down devices 121-124, and optionally additional controlsignals to the amplitude control circuitry 130 and 132, as indicated bythe dotted lines in FIG. 2. The digital control and envelope detectors134 and 136 may also optionally be coupled to process monitor blocksand/or duty cycle distortion monitor blocks. The digital control andenvelope detectors 134 and 136 may, for example, interact with processmonitor blocks that provide information about the process technologyoperates, e.g. how threshold voltage or switching speed of theimplemented PMOS/NMOS transistors compare to those in a typical process.In some embodiments, the digital control and envelope detectors 134 and136 may interact with ring oscillators to provide information about thespeed of NMOS and PMOS transistors implemented in the same process onthe same chip common to the VCO. For example, some embodiments mayutilize process monitors comprising ring oscillators made of the sametype of PMOS and NMOS transistors as in the VCO. In other embodiments,the digital control and envelope detectors 134 and 136 may interact withother types of process monitoring circuits.

The two outputs V₊ and V⁻ are also applied to the digital control andenvelope detectors 134, 136. The envelope detector circuits determinethe amplitude of the VCO output. Digital control logic uses the envelopedetector information concerning the VCO amplitude to determine whenoscillation has reliably been established in order to disable commonmode adjustment circuitry. Alternatively, the control logic may adjustcommon mode voltage for a prescribed time in a prescribed direction thatis known based on, for example, off-line testing or a priori analysisand simulation of NMOS and PMOS process corners to ensure reliable VCOstart-up.

If desired, devices 121-124 can be configured to perform a useful butoptional secondary function. Mismatch in core devices 111-114 and/ortank capacitance 116 may result in a small DC differential offsetbetween V₊ and V⁻ that should ideally be zero and/or a common modevoltage that is not optimally placed at one half the supply voltage. Insome embodiments, the digital control and envelope detectors 134 and 136are configured to detect any duty cycle distortion (DCD), or otherparameters such as, for example, average voltage level (DC component),to detect imbalance in the signals at V₊/V⁻. Some combination of thepull-up/pull-down devices 121-124 connected across the common nodes 117and 118 to V₊/V⁻ can be enabled to adjust the DC voltage at V₊/V⁻,thereby improving the match between the rise and fall times of thepositive and negative output signals and/or the match betweencomplementary pairs at the cost of increased power consumption. Theamount of adjustment possible would depend on the size of devices121-124 and/or the frequency shift that can be tolerated while thesedevices are enabled. Better matching of V₊/V⁻ also improves common-modenoise rejection, including power supply rejection (PSR). Better symmetryof the rise and fall transitions driven by the PMOS and NMOS transistorsimproves close-in 1/f³ noise, as postulated in the Hajimiri et al.reference noted earlier in the “Background” section.

The amplitude control blocks 130, 132 may be used to reduce VCO powerconsumption after start-up. When the temporary common mode voltageadjustment operation is underway, the amplitude control blocks 130, 132can be set to minimize their voltage drop and maximize bias current,aiding in gain enhancement to help start up the oscillation.Alternatively or additionally, the amplitude control blocks 130, 132 canbe used in tandem with the envelope detection circuitry 134, 136 duringsteady-state operation to reduce power consumption and act as asecondary means of common mode voltage control, as indicated by thedotted lines in FIG. 2.

Other embodiments can provide substantially the same functionality usingalternative circuitry. FIG. 3 shows an example circuit 200 having a VCOcore 210, comprising elements 211-218, which correspond to 111-118described above, connected to V_(DD) through a programmable low-dropout(LDO) voltage regulator 238. The VCO core 210 is connected to groundthrough an amplitude control block 232 and the common mode voltage at217, 218 is provided to a digital control and envelope detector 234. Thea digital control and envelope detector 234 may be similar to, thedigital control and envelope detectors 134 and 136 discussed above, andsimilarly optionally interface with process monitor blocks and/or dutycycle distortion monitor blocks as described above. The LDO voltageregulator 238 is controlled by a software and/or firmware and/orhardware sequencer 237 based on signals from the digital control andenvelope detector 234 to temporarily shift up the voltage of the powersupply to the VCO core 210, and thus common mode voltage at 217, 218, toa level that is sufficient to initiate oscillation. Once steady-statehas been established (e.g., after a predetermined time, or based on adetermination of stead-state by one or more envelope detector circuitsin 234), the LDO voltage regulator 238 returns the power supply voltageto the “normal” low supply-voltage mode to reduce power consumption andprevent long-term Electrical Overstress (EOS) of the transistors211-214. Because the voltage shift is short-term, long-term reliabilityand life time of the transistor devices 211-214 are substantiallyunaffected.

Although the example embodiments of FIGS. 2 and 3 are each implementedwith a complementary cross-coupled LC VCO, techniques for pulsing and/orshifting common mode voltage to temporarily increase PMOS and/or NMOSgain could also be applied to other oscillator circuits, for exampleother LC VCO topologies.

FIG. 4A shows an example circuit 300 having a VCO core 340 comprising asingle pair of NMOS transistors 341 and 342 cross-coupled across commonnodes 347, 348 of an LC tank comprising inductors 343, 344 and variablecapacitor 346. A center tap 345 of the inductors 343, 344 is connectedto a steady-state power supply providing a lower voltage (e.g. V_(DD)_(_) _(SMALL), which may be V_(DD)/2 in some embodiments) than a nominalpower supply voltage V_(DD) through an amplitude control block 350. Thesources of the NMOS devices 341, 342 are connected to ground throughanother amplitude control block 352. A pair of pull-up transistors 355,357 are controlled to selectively connect V₊, V⁻ to V_(DD) by controlblocks 354, 356. In some embodiments, V₊ and V⁻ are also provided to thecontrol blocks 354, 356 for monitoring and fine tuning the common modevoltage during steady-state oscillation. For example, some embodimentsmay measure the average level (DC component) of V+ and V− using anysuitable voltage monitor (e.g. an average detector) to determine thecommon mode voltage and/or voltage on each of V+ and V− so that thecontrol blocks 354, 356 adjust the pull-up transistors to provide anydesired fine tuning.

FIG. 4B shows an example circuit 400 having a VCO core 460 comprising asingle pair of PMOS transistors 461 and 462 cross-coupled across commonnodes 467, 468 of an LC tank comprising inductors 463, 464 and variablecapacitor 466. The sources of the PMOS devices 461, 462 are connected toa steady-state power supply providing a lower voltage (e.g. V_(DD) _(_)_(SMALL), which may be V_(DD)/2 in some embodiments) than a nominalpower supply voltage V_(DD) through an amplitude control block 470. Acenter tap 465 of the inductors 463, 464 is connected to ground throughanother amplitude control block 472. A pair of pull-down transistors475, 477 are controlled to selectively connect V₊, V⁻ to a negativesupply voltage V_(DD) _(_) _(NEG) by control blocks 354, 356. Thenegative supply voltage V_(DD) _(_) _(NEG) may be any voltage level lowenough to start the oscillation and or adjust common mode voltage asnecessary. In some embodiments, V₊ and V⁻ are also provided to thecontrol blocks 474, 476 for monitoring and fine tuning the common modevoltage during steady-state oscillation. For example, some embodimentsmay measure the average level (DC component) of V+ and V− using anysuitable voltage monitor (e.g. an average detector) to determine thecommon mode voltage and/or voltage on each of V+ and V− so that thecontrol blocks 474, 476 adjust the pull-down transistors to provide anydesired fine tuning.

FIG. 5 shows an example method 500 that may be carried out by a hardwareand/or firmware and/or software sequencer to execute the series ofoperations required to initiate oscillation and detect steady-state. Aprocess monitor is first enabled 502. The process monitor may be but isnot necessarily NMOS-only and/or PMOS-only ring oscillator(s). In someembodiments, ring oscillator frequency is measured and compared againstpredetermined values. Other embodiments may measure and compare otherparameters, e.g. threshold voltages of NMOS and PMOS transistors, todetermine process and voltage conditions. The result of this comparisonis used to identify 504 the transistor process and voltagecharacteristics (i.e. fast, slow, or typical, respectively,corresponding to processes with lower than nominal, higher than nominal,or nominal threshold voltage for MOS transistors). In implementationsusing both PMOS and NMOS transistors, process characteristics areidentified 504 for each of the PMOS and NMOS transistor types. Based onthe identified process characteristics, the appropriate common modeand/or differential voltage is forced 506 to temporarily increase PMOSand/or NMOS transconductance gain. Common mode voltage forcing 506continues to be enabled until steady-state oscillation is detected 508,at which point voltage forcing is disabled 510 and the VCO enters normaloperation. During normal operation, the VCO amplitude and/or common modevoltage and/or frequency and/or duty cycle distortion is optionallycontinuously detected 512 and adjusted 514 to maintain desiredperformance and/or functionality.

Example applications: Circuits and methods according to the presentdisclosure may be implemented in any system that uses a CSU or PLL togenerate a clock signal, including but not limited to RF applications,telecommunication and data transmission applications, and digital signalprocessing applications. Certain embodiments provide one or more offollowing advantages in such applications:

The option to reduce cost in CSU or PLL systems by eliminating the needto use low-voltage threshold (LVT) or ultra-low-voltage threshold (ULVT)devices in CMOS technology nodes that offer these device options at anincreased mask price over standard threshold voltage (SVT) devices.

The ability to improve VCO start-up with respect to robustness and/orfaster starting time in technology nodes where device threshold voltagesare such that oscillator loop gain is too low to reliably entersteady-state operation across all process, voltage, and temperature(PVT) corners.

The ability to improve the reliability of VCO start-up without the needto increase loop gain by increasing transistor device size (width), thusminimizing parasitic capacitance and maximizing VCO frequency andfrequency tuning range (FTR).

The ability to improve the reliability of VCO start-up without the needto increase loop gain by increasing transistor device size (width)and/or bias current, thus saving power.

The ability to improve the reliability of VCO start-up without the needto increase supply voltage at steady-state operation, thus saving power.This translates to cost saving in mobile and/or battery-operatedapplications, when battery size (capacity and/or nominal voltage) can bereduced.

Circuits designed according to some embodiments allow significantreduction in the cost of producing large Clock Synthesizer systems thatcontain one or more PLLs, or in other LC oscillator applications, byremoving the need for low-voltage threshold or ultra-low-voltagethreshold PMOS/NMOS transistors in a CMOS process technology, and/or byreducing required power supply voltage and current draw in normal(steady-state) operation.

The above-described embodiments are intended to be examples only.Alterations, modifications and variations can be effected to theparticular embodiments by those of skill in the art without departingfrom the scope, which is defined solely by the claims appended hereto.

1. An apparatus comprising: a voltage controlled oscillator (VCO) havingan LC tank and at least one pair of transistors cross-coupled across apair of common nodes of the LC tank, with a drain of one transistor ofthe pair and a gate of the other transistor of the pair connected to oneof the pair of common nodes of the LC tank, and a gate of the onetransistor of the pair and a drain of the other transistor of the pairconnected to the other of the pair of common nodes of the LC tank; apower supply system comprising a voltage supply coupled to a low-dropout(LDO) voltage regulator; a control circuit coupled to monitor the pairof common nodes, the control circuit comprising: a sequencer coupled tothe LDO voltage regulator to control the LDO voltage regulator to:provide a first supply voltage to the VCO such that a voltage differencebetween a common mode voltage at the pair of common nodes and a sourcevoltage of transistors of the pair of transistors is less than athreshold voltage of the transistors of the pair of transistors; providea second supply voltage higher than the first supply voltage to the VCOto temporarily adjust the common mode voltage to increase the voltagedifference and initiate differential oscillation in the VCO at thecommon nodes, the second supply voltage being provided until the controlcircuit determines steady-state oscillation is established; and providethe first supply voltage to the VCO once the control circuit determinessteady-state oscillation is established thereby reducing powerconsumption while sustaining the oscillation.
 2. An apparatus accordingto claim 1, wherein the control circuit further comprises a processmonitor coupled to detect process and voltage conditions at the commonnodes of the VCO, the process monitor also coupled to the sequencer. 3.An apparatus according to claim 2, wherein the VCO comprises twocomplementary pairs of cross-coupled transistors, with one of thecomplementary pairs comprising a pair of NMOS transistors and the otherof the complementary pairs comprising a pair of PMOS transistors,wherein the control circuit is configured to: increase the common modevoltage independently of the LDO voltage regulator in response to thedetected process and voltage conditions indicating that the voltagedifference is less than a transistor threshold voltage of the pair ofNMOS transistors; and decrease the common mode voltage independently ofthe LDO voltage regulator in response to the detected process andvoltage conditions indicating that the voltage difference is less than atransistor threshold voltage of the pair of PMOS transistors.
 4. Anapparatus according to claim 3, wherein the control circuit furthercomprises: a pair of pull-up transistors coupled between the pair ofcommon nodes and a pull-up supply voltage higher than the first supplyvoltage; and a pair of pull-down transistors coupled between the pair ofcommon nodes and one of ground and a negative supply voltage, whereinthe control circuit is further configured to selectively: increase thecommon mode voltage by selectively activating the pair of pull-uptransistors; and decrease the common mode voltage by selectivelyactivating the pair of pull-down transistors.
 5. An apparatus accordingto claim 2, wherein the process monitor comprises at least one ringoscillator on an integrated circuit chip common to the VCO, and wherethe at least one ring oscillator is made of the same type of PMOS andNMOS transistors as in the VCO.
 6. An apparatus according to claim 1,wherein the VCO comprises a single pair of NMOS transistorscross-coupled across the common nodes, wherein the first supply voltageis provided by the LDO voltage regulator to a center tap of an inductorof the LC tank, and wherein the control circuit comprises a pair ofpull-up transistors coupled between the pair of common nodes and apull-up supply voltage higher than the first supply voltage.
 7. Anapparatus according to claim 1, wherein the VCO comprises a single pairof PMOS transistors cross-coupled across the common nodes, wherein thefirst supply voltage is provided by the LDO voltage regulator to thePMOS transistors, and a center tap of an inductor of the LC tank isgrounded while powering the VCO during steady-state oscillation, andwherein the control circuit comprises a pair of pull-down transistorscoupled between the pair of common nodes and a negative supply voltage.8. An apparatus according to claim 1, wherein the control circuit isconfigured to monitor oscillations at the pair of common nodes duringsteady-state oscillation and adjust the common mode voltage to improvematching of rising and falling transitions of signals at the pair ofcommon nodes.
 9. An apparatus according to claim 1, wherein the controlcircuit is configured to adjust the common mode voltage for apredetermined time period and to a predetermined voltage level whentemporarily adjusting the common mode voltage.
 10. An apparatusaccording to claim 1, wherein the control circuit is configured tomonitor the pair of common nodes, and adjust the common mode voltage andretain the adjusted common mode voltage until steady-state oscillationis detected.
 11. A method of controlling a voltage controlled oscillator(VCO) having an LC tank and at least one pair of transistorscross-coupled across a pair of common nodes of the LC tank, with a drainof one transistor of the pair and a gate of the other transistor of thepair connected to one of the pair of common nodes of the LC tank, and agate of the one transistor of the pair and a drain of the othertransistor of the pair connected to the other of the pair of commonnodes of the LC tank, the method comprising: monitoring the pair ofcommon nodes with a control circuit; controlling a low-dropout (LDO)voltage regulator with a sequencer, the controlling comprising:providing a first supply voltage to the VCO such that a voltagedifference between a common mode voltage at the pair of common nodes anda source voltage of transistors of the pair of transistors is less thana threshold voltage of the transistors of the pair of transistors;providing a second supply voltage higher than the first supply voltageto the VCO to temporarily adjust the common mode voltage to increase thevoltage difference and initiate differential oscillation in the VCO atthe common nodes, the second supply voltage being provided until thecontrol circuit determines steady-state oscillation is established; andproviding the first supply voltage to the VCO once the control circuitdetermines steady-state oscillation is established thereby reducingpower consumption while sustaining the oscillation.
 12. A methodaccording to claim 11, further comprising detecting process and voltageconditions at the common nodes of the VCO with a process monitor.
 13. Amethod according to claim 12, wherein the VCO comprises twocomplementary pairs of cross-coupled transistors, with one of thecomplementary pairs comprising a pair of NMOS transistors and the otherof the complementary pairs comprising a pair of PMOS transistors,wherein the method further comprises: increasing the common mode voltageindependently of the LDO voltage regulator in response to the detectedprocess and voltage conditions indicating that the voltage difference isless than a transistor threshold voltage of the pair of NMOStransistors; and decreasing the common mode voltage independently of theLDO voltage regulator in response to the detected process and voltageconditions indicating that the voltage difference is less than atransistor threshold voltage of the pair of PMOS transistors.
 14. Amethod according to claim 13, wherein the control circuit comprises: apair of pull-up transistors coupled between the pair of common nodes anda pull-up supply voltage higher than the first supply voltage; and apair of pull-down transistors coupled between the pair of common nodesand one of ground and a negative supply voltage, wherein the methodfurther comprises selectively: increasing the common mode voltage byselectively activating the pair of pull-up transistors; and decreasingthe common mode voltage by selectively activating the pair of pull-downtransistors.
 15. A method according to claim 12, wherein the processmonitor comprises at least one ring oscillator on an integrated circuitchip common to the VCO, and where the at least one ring oscillator ismade of the same type of PMOS and NMOS transistors as in the VCO.
 16. Amethod according to claim 11, wherein the VCO comprises a single pair ofNMOS transistors cross-coupled across the common nodes, wherein themethod further comprises providing the first supply voltage by the LDOvoltage regulator to a center tap of an inductor of the LC tank, andwherein the control circuit comprises a pair of pull-up transistorscoupled between the pair of common nodes and a pull-up supply voltagehigher than the first supply voltage.
 17. A method according to claim11, wherein the VCO comprises a single pair of PMOS transistorscross-coupled across the common nodes, wherein the method furthercomprises providing the first supply voltage by the LDO voltageregulator to the PMOS transistors, and a center tap of an inductor ofthe LC tank is grounded while powering the VCO during steady-stateoscillation, and wherein the control circuit comprises a pair ofpull-down transistors coupled between the pair of common nodes and anegative supply voltage.
 18. A method according to claim 11, furthercomprising monitoring oscillations at the pair of common nodes duringsteady-state oscillation and adjusting the common mode voltage toimprove matching of rising and falling transitions of signals at thepair of common nodes.
 19. A method according to claim 11, furthercomprising adjusting the common mode voltage for a predetermined timeperiod and to a predetermined voltage level when temporarily adjustingthe common mode voltage.
 20. A method according to claim 11, furthercomprising monitoring the pair of common nodes, and adjusting the commonmode voltage and retaining the adjusted common mode voltage untilsteady-state oscillation is detected.